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 HCF40182B
LOOK-AHEAD CARRY GENERATOR
s
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GENERATES HIGH-SPEED CARRY ACROSS FOUR ADDERS OR ADDER GROUPS HIGH-SPEED OPERATIONAL: tPHL = tPLH = 100 ns (typ.) AT VDD = 10V CASCADABLE FOR FAST CARRIES OVER N BITS DESIGNED FOR USE WITH HCF40181B ALU STANDARDIZED, SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT CURRENT SPECIFIED UP TO 20V INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES"
DIP
SOP
ORDER CODES
PACKAGE DIP SOP TUBE HCF40182BEY HCF40182BM1 T&R HCF40182M013TR
DESCRIPTION HCF40182B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. He is a high speed look-ahead carry generator capable of anticipating a carry across four binary adders or adder groups. HCF40182B is cascadable to perform full look-ahead across n-bit adders. Carry propagate-carry, and generate-carry functions are provided as PIN CONNECTION
enumerated in the terminal designation below. HCF40182B, when used in conjunction with the HCF40181B arithmetic logic unit (ALU), provides full high-speed look-ahead carry capability for up to n-bit words. Each HCF40182B generates the look-ahead (anticipated carry) across a group of four ALUs. In addition, other HCF40182Bs may be emplayed to anticipate the carry across sections of four look-ahead blocks up to n-bits.
September 2002
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HCF40182B
IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 3, 1, 14, 5 4, 2, 15, 6 13 12, 11, 9 10 7 8 16 SYMBOL G0 to G3 P0 to P3 NAME AND FUNCTION Carry Generate Inputs (Active LOW) Carry Propagate Inputs (Active LOW) Active-high Carry Input
Cn Cn+x, Cn+y, Active-high Carry Outputs Cn+z Carry Propagate Output G (Active LOW) Carry Generate Output P (Active LOW) Vss Negative Supply Voltage Vdd Positive Supply Voltage
FUNCTIONAL DIAGRAM
TRUTH TABLES FOR G OUTPUT
INPUTS G3 L X X X G2 X L X X G1 G0 P3 P2 X X L L P1 X X X L OUTPUT G L L L L H
X X X X X L L X L X L L ALL OTHER COMBINATIONS
FOR P OUTPUT
INPUTS P3 L P2 P1 P0 L OUTPUT P L H
L L ALL OTHER COMBINATIONS
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HCF40182B
FOR Cn+x OUTPUT
INPUTS G0 L X P0 X L ALL OTHER COMBINATIONS Cn X H OUTPUT Cn+x H H L
FOR Cn+y OUTPUT
INPUTS G1 L X X G0 X L X P1 X L L ALL OTHER COMBINATIONS P0 X X L Cn X X H OUTPUT Cn+y H H H L
FOR Cn+z OUTPUT
INPUTS G2 L X X X G1 X L X X GO P2 P1 P0 X X X L Cn X X X H OUTPUT Cn+z H H H H L
X X X X L X L L L X L L ALL OTHER COMBINATIONS
X : Don't Care Cn+x = G0+P0Cn Cn+y = G1+P1G0+P1P0Cn Cn+z = G2+P2G1+P2P1G0+P2P1P0Cn G = G3+G3+P3G2+P3P2G1+P3P2P1G0 P = P3P2P1P0 or Cn+x = Y0+(X0+Cn) Cn+y = Y1+[X1+Y0(X0+Cn)] Cn+z = Y2+{X2+Y1[X1+Y0(X0+Cn)]} G = Y3+(X3+Y2)(X3+X2+Y1)(X3+X2+X1+Y0) P = X3+X2+X1+X0
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HCF40182B
LOGIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol VDD VI II PD Top Tstg Supply Voltage DC Input Voltage DC Input Current Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature Storage Temperature Parameter Value -0.5 to +22 -0.5 to VDD + 0.5 10 200 100 -55 to +125 -65 to +150 Unit V V mA mW mW C C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol VDD VI Top Supply Voltage Input Voltage Operating Temperature Parameter Value 3 to 20 0 to VDD -55 to 125 Unit V V C
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HCF40182B
DC SPECIFICATIONS
Test Conditions Symbol Parameter VI (V) 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 0.5/4.5 1/9 1.5/18.5 0.5/4.5 9/1 1.5/18.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 VO (V) IO VDD (A) (V) 5 10 15 20 5 10 15 5 10 15 5 10 15 5 10 15 5 5 10 15 5 10 15 18 TA = 25C Min. Typ. 0.04 0.04 0.04 0.08 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 -1.36 -0.44 -1.1 -3.0 0.44 1.1 3.0 -3.2 -1 -2.6 -6.8 1 2.6 6.8 10-5 5 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 3.5 7 11 1.5 3 4 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 Max. 5 10 20 100 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 Value -40 to 85C Min. Max. 150 300 600 3000 4.95 9.95 14.95 0.05 0.05 0.05 -55 to 125C Min. Max. 150 300 600 3000 Unit
IL
Quiescent Current
A
VOH
High Level Output Voltage Low Level Output Voltage High Level Input Voltage Low Level Input Voltage Output Drive Current
VOL
VIH
VIL
<1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1
V
V
V
V
IOH
IOL
Output Sink Current Input Leakage Current Input Capacitance
0/5 0/5 0/10 0/15 0/5 0/10 0/15 0/18
mA
mA
II
any input any input
0.1
7.5
1
1
A
pF
CI
The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25C, CL = 50pF, RL = 200K, tr = tf = 20 ns)
Test Condition Symbol Parameter VDD (V) 5 10 15 5 10 15 5 10 15 See Timing Chart Min. Value (*) Typ. 200 100 75 240 120 90 100 50 40 Max. 400 200 150 480 240 180 200 100 80 ns Unit
tPLH tPHL Propagation Delay Time P, G, in to P G Out and Carry Outs tPLH tPHL Cn to Carry Outputs
ns
tTHL tTLH Transition Time
ns
(*) Typical temperature coefficient for all VDD value is 0.3 %/C.
5/10
HCF40182B
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and probe capacitance) RL = 200K RT = ZOUT of pulse generator (typically 50)
WAVEFORM : PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle)
6/10
HCF40182B
TYPICAL APPLICATION: 16-BIT TWO- LEVEL LOOK-AHEAD ALU
TYPICAL APPLICATION: 64-BIT FULL CARRY LOOK-AHEAD ALU IN 3 LEVELS
TYPICAL APPLICATION: COMBINED TWO-LEVEL LOOK-AHEAD AND RIPPLE-CARRY ALU
7/10
HCF40182B
Plastic DIP-16 (0.25) MECHANICAL DATA
mm. DIM. MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 TYP. MAX. inch
P001C
8/10
HCF40182B
SO-16 MECHANICAL DATA
DIM. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8 (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45 (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm. MIN. TYP MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.003 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010
PO13H
9/10
HCF40182B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. (c) http://www.st.com
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